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|Title:||Design space exploration for arbitrary FPGA architectures||Authors:||Lee, C.S.
|Issue Date:||2005||Citation:||Lee, C.S.,Ha, Y. (2005). Design space exploration for arbitrary FPGA architectures. ICESS 2005 - Second International Conference on Embedded Software and Systems 2005 : 269-275. ScholarBank@NUS Repository. https://doi.org/10.1109/ICESS.2005.46||Abstract:||With increasingly diverse demands being placed on FPGA technology by a wide variety of applications, the need for CAD tools to design more arbitrary FPGA architectures naturally fits in. This allows researchers to design optimal architectures in terms of area, performance, power and cost or other metrics. To satisfy this need, we design a FPGA architecture design space exploration environment which makes use of a graphical user interface (GUI). This interface allows users to specify basic and up-front parameters to describe any heterogeneous FPGA routing architecture. Before finalizing the architecture, the freedom to edit the architecture is given. Automatic generation of an internal routing resource graph (RRG)for the user-defined routing architecture is then carried out to enable the placement and routing. By allowing FPGA researchers to freely define the routing architectures using high level parameter description and low level manual customization, they obtain more flexibility and efficiency in design space exploration. © 2005 IEEE.||Source Title:||ICESS 2005 - Second International Conference on Embedded Software and Systems||URI:||http://scholarbank.nus.edu.sg/handle/10635/69879||ISBN:||0769525121||DOI:||10.1109/ICESS.2005.46|
|Appears in Collections:||Staff Publications|
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