Please use this identifier to cite or link to this item:
|Title:||Design and analysis of a high-speed comparator||Authors:||Jun, G.
Bipolar IC design
Flash ADC design
High-speed comparator design
|Issue Date:||2005||Citation:||Jun, G.,Yong, L.,Bo, S. (2005). Design and analysis of a high-speed comparator. Proceedings - 2005 IEEE International Workshop on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, RFIT 2005 2005 : 215-218. ScholarBank@NUS Repository. https://doi.org/10.1109/RFIT.2005.1598914||Abstract:||This paper presents the design and analysis of an ultra high-speed bipolar comparator based on master-slave architecture. The comparator can be used for very high speed data converters design. Master-slave structure is used to improve metastability behavior and reduce minimum differential input voltage. Implemented in a 0.35-μm SiGe BiCMOS process, the comparator consumes approximately 70mW with sampling speed of 16GHz and resolvable minimum input voltage of 8mV peak-to-peak.||Source Title:||Proceedings - 2005 IEEE International Workshop on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, RFIT 2005||URI:||http://scholarbank.nus.edu.sg/handle/10635/69814||ISBN:||0780393724||DOI:||10.1109/RFIT.2005.1598914|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Oct 20, 2019
checked on Oct 13, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.