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dc.titleCharacterization and modeling of CMOS on-chip coupled interconnects
dc.contributor.authorKumar, R.
dc.contributor.authorRustagi, S.C.
dc.contributor.authorKang, K.
dc.contributor.authorMouthaan, K.
dc.contributor.authorWong, T.K.S.
dc.identifier.citationKumar, R., Rustagi, S.C., Kang, K., Mouthaan, K., Wong, T.K.S. (2008). Characterization and modeling of CMOS on-chip coupled interconnects. ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference : 159-162. ScholarBank@NUS Repository.
dc.description.abstractIn this paper, an S-parameter measurement based modeling methodology is proposed for characterization of coupled interconnects on silicon substrate. First, a set of single transmission lines in ground-signal-ground configuration is measured and modeled as multiple Γ-sections. A pair of coupled lines is then modeled as two single lines interconnected by coupling capacitance, mutual inductance and mutual resistance. Asymptotic techniques and closed-form analytical expressions are used to determine the initial guesses for optimization of the model parameters of single and coupled lines. It is found that in extending the single line model to the coupled lines, only a couple of model parameters need to change due to the proximity effect. Further, the time-domain crosstalk is measured for Cu/oxide and Cu/Ultra low-κ interconnects and analyzed using the proposed model. Good agreement is found between the simulated and measured results in both the frequency and the time domains for different lengths, widths and spacing (for coupled-lines) confirming the accuracy of the modeling methodology. The compact modeling approach presented here facilitates accurate characterization and modeling of coupled interconnects based on measured S-parameters data. © 2007 IEEE.
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference
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