Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/69290
DC Field | Value | |
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dc.title | An asymmetrical half bridge DC-DC converter : Close loop design in frequency domain | |
dc.contributor.author | Xu, X. | |
dc.contributor.author | Khambadkone, A.M. | |
dc.contributor.author | Oruganti, R. | |
dc.date.accessioned | 2014-06-19T02:59:00Z | |
dc.date.available | 2014-06-19T02:59:00Z | |
dc.date.issued | 2004 | |
dc.identifier.citation | Xu, X.,Khambadkone, A.M.,Oruganti, R. (2004). An asymmetrical half bridge DC-DC converter : Close loop design in frequency domain. PESC Record - IEEE Annual Power Electronics Specialists Conference 2 : 1642-1647. ScholarBank@NUS Repository. | |
dc.identifier.issn | 02759306 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/69290 | |
dc.description.abstract | In this paper, the small signal model analysis of an Asymmetrical Half-Bridge DC-DC Converter (AHBC) operating in the continuous conduction mode (CCM) is presented. The influence of the non-ideal components to the system performance is discussed. Based on the small signal model, the close loop feedback is designed in the frequency domain for a PI controller and a lead-lag controller. The design criteria for the close loop feedback is described and a clear design process for the feedback compensator is presented. How to achieve the optimum bandwidth and phase margin under the influence of the complicated system structure is investigated. The close loop system load dynamic response from a 12V/4A experiment circuit is obtained. | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.sourcetitle | PESC Record - IEEE Annual Power Electronics Specialists Conference | |
dc.description.volume | 2 | |
dc.description.page | 1642-1647 | |
dc.description.coden | PRICD | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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