Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/69063
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dc.titleA sequential reoptimization approach for the design of signed power-of-two coefficient lattice QMF bank
dc.contributor.authorYu, Y.J.
dc.contributor.authorLim, Y.C.
dc.date.accessioned2014-06-19T02:56:25Z
dc.date.available2014-06-19T02:56:25Z
dc.date.issued2001
dc.identifier.citationYu, Y.J.,Lim, Y.C. (2001). A sequential reoptimization approach for the design of signed power-of-two coefficient lattice QMF bank. IEEE Region 10 International Conference on Electrical and Electronic Technology : 57-60. ScholarBank@NUS Repository.
dc.identifier.isbn0780371011
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69063
dc.description.abstractThis paper presents a sequential optimization approach for the design of lattice structure quadrature mirror filter (QMF) banks subject to the sum of signed power-of-two (SPT) coefficient constraints. The lattice structure QMF bank structurally guarantees the perfect reconstruction (PR) property. Nevertheless, its frequency response is still adversely affected by coefficient quantization. In this paper, a frequency response deterioration measure is developed from the lattice coefficient analysis. Based on this frequency response deterioration measure, the coefficient which will cause the largest deterioration in the frequency response of the filter is selected for quantization first. After the coefficient is quantized, the remaining unquantized coefficients are reoptimized. The process of quantizing the coefficient and reoptimizing the remaining unquantized coefficient is repeated until all the coefficients are quantized. The frequency responses of the filters obtained using oar algorithm are significantly superior to those obtained by simple rounding of the coefficient values.
dc.sourceScopus
dc.subjectPerfect Reconstruction
dc.subjectQuadrature Mirror Filter
dc.subjectSensitivity Measure
dc.subjectSigned Power-of-two
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleIEEE Region 10 International Conference on Electrical and Electronic Technology
dc.description.page57-60
dc.identifier.isiutNOT_IN_WOS
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