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|Title:||A runtime auto scalable Power-Efficient Instruction-Cache design||Authors:||Tiow, T.T.
|Issue Date:||2005||Citation:||Tiow, T.T.,Xiaoping, Z. (2005). A runtime auto scalable Power-Efficient Instruction-Cache design. Proceedings - IEEE International Symposium on Circuits and Systems : 5270-5273. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS.2005.1465824||Abstract:||With the trend towards larger on-chip cache memories in microprocessors, both dynamic and static power reduction in such units has attracted more research interest. Since the required cache size is different widely across and within programs, we propose an algorithm that adds some special memory scaling instructions (MSIs) to the object codes to track the working set size during compilation phase. According to the MSIs and the current system state, a hardware controller makes the decision of caching instructions and scaling the size of I-cache memory. Thus the unused cache lines can be switched off at runtime and some instructions may bypass from loading into I-cache to save power. Experimental results using popular Windows-based applications show that this strategy can save 67.3% of energy in a 32K I-cache with only 2.8% of performance degradation on average. © 2005 IEEE.||Source Title:||Proceedings - IEEE International Symposium on Circuits and Systems||URI:||http://scholarbank.nus.edu.sg/handle/10635/69051||ISSN:||02714310||DOI:||10.1109/ISCAS.2005.1465824|
|Appears in Collections:||Staff Publications|
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