Please use this identifier to cite or link to this item: https://doi.org/10.1109/IPDPSW.2012.23
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dc.titleA power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs
dc.contributor.authorLoke, W.T.
dc.contributor.authorHa, Y.
dc.contributor.authorZhao, W.
dc.date.accessioned2014-06-19T02:55:49Z
dc.date.available2014-06-19T02:55:49Z
dc.date.issued2012
dc.identifier.citationLoke, W.T., Ha, Y., Zhao, W. (2012). A power and cluster-aware technology mapping and clustering scheme for dual-VT FPGAs. Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012 : 221-226. ScholarBank@NUS Repository. https://doi.org/10.1109/IPDPSW.2012.23
dc.identifier.isbn9780769546766
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69009
dc.description.abstractIn this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric VT through RBB offer the potential of reducing leakage power with minimal or no sacrifice to circuit speed. Today, Altera's Stratix line of FPGAs deploy a similar strategy, but with optimizations limited to the post-P&R stage. We present a novel two-stage technology mapping (RBBMap) and logic block packing (RBBPack) tool that is free from clustering constraints limiting the post-P&R method, and moves RBB optimizations upwards to the technology mapping level. Using the baseline technology mapping tool Emap, our tools generate an average of 70.95% savings in logic block leakage power and 28.30% savings in total energy consumption. © 2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/IPDPSW.2012.23
dc.sourceScopus
dc.subjectDual-VT
dc.subjectEDA
dc.subjectFPGA
dc.subjectProgrammable-VT
dc.subjectReverse Back Bias
dc.subjectTechnology Mapping
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/IPDPSW.2012.23
dc.description.sourcetitleProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
dc.description.page221-226
dc.identifier.isiut000309409400020
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