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|Title:||A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs||Authors:||Singh, A.K.
|Issue Date:||2011||Citation:||Singh, A.K.,Kumar, A.,Srikanthan, T. (2011). A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 : 175-184. ScholarBank@NUS Repository. https://doi.org/10.1145/2038698.2038726||Abstract:||Modern embedded systems are based on Multiprocessor- Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at runtime subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the runtime mapping is speeded up by 93% when compared to state-of-the-art techniques. Copyright © 2011 ACM.||Source Title:||Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11||URI:||http://scholarbank.nus.edu.sg/handle/10635/68843||ISBN:||9781450307130||DOI:||10.1145/2038698.2038726|
|Appears in Collections:||Staff Publications|
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