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|Title:||A design flow for partially reconfigurable heterogeneous multi-processor platforms||Authors:||Li, J.
Partially reconfigurable systems
|Issue Date:||2012||Citation:||Li, J.,Das, A.,Kumar, A. (2012). A design flow for partially reconfigurable heterogeneous multi-processor platforms. Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP : 170-176. ScholarBank@NUS Repository. https://doi.org/10.1109/RSP.2012.6380707||Abstract:||Modern multiprocessor systems-on-chip (MPSoCs) are expected to handle multi-application usecases. As the number and complexity of these applications scale, resource allocation to meet the application throughput requirement is becoming quite a challenge. In this paper, a complete design flow is proposed for partially reconfigurable heterogeneous MPSoC platforms. The proposed flow determines the minimum resources required to map and guarantee the throughput of applications in all use-cases. Further, a suitable mapping for each application is chosen so that energy consumption is minimized. Experiments conducted with a set of synthetic benchmarks and real-life applications clearly demonstrate the advantage of our approach over homogeneous or fully reconfigurable designs. The proposed design flow achieves more than 50% energy savings when the number of configurations is not optimized. With configuration-optimization, our flow results in 75% reduction in the number of configurations with 5% reduction in energy. ©2012 IEEE.||Source Title:||Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP||URI:||http://scholarbank.nus.edu.sg/handle/10635/68773||ISBN:||9781467327862||ISSN:||21505500||DOI:||10.1109/RSP.2012.6380707|
|Appears in Collections:||Staff Publications|
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