Please use this identifier to cite or link to this item:
https://doi.org/10.1109/MWSCAS.2007.4488614
DC Field | Value | |
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dc.title | A 1 GHz decimation filter for Sigma-Delta ADC | |
dc.contributor.author | Lian, Y. | |
dc.contributor.author | Wei, Y. | |
dc.contributor.author | Chandrasekaran, R. | |
dc.date.accessioned | 2014-06-19T02:52:12Z | |
dc.date.available | 2014-06-19T02:52:12Z | |
dc.date.issued | 2007 | |
dc.identifier.citation | Lian, Y.,Wei, Y.,Chandrasekaran, R. (2007). A 1 GHz decimation filter for Sigma-Delta ADC. Midwest Symposium on Circuits and Systems : 401-404. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/MWSCAS.2007.4488614" target="_blank">https://doi.org/10.1109/MWSCAS.2007.4488614</a> | |
dc.identifier.isbn | 1424411769 | |
dc.identifier.issn | 15483746 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/68696 | |
dc.description.abstract | This paper presents the implementation of a high-speed decimation filter operating at Giga Hertz that is suitable for high-speed Delta-Sigma analog-to-digital converters. The filter is realized in a non-recursive architecture using a novel full adder and D flip-flop. The filter has been implemented in a 0.18μm/ 1.8 V CMOS technology for a decimation factor of 4. The operation frequency is 1 GHz and the power consumption of I and Q filters are 6 mW and 4 mW, respectively. © 2007 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/MWSCAS.2007.4488614 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/MWSCAS.2007.4488614 | |
dc.description.sourcetitle | Midwest Symposium on Circuits and Systems | |
dc.description.page | 401-404 | |
dc.description.coden | MSCSD | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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