Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/62871
DC Field | Value | |
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dc.title | Theory for the determination of backside contact resistance of semiconductor wafers from surface potential measurements | |
dc.contributor.author | Tan, L.S. | |
dc.contributor.author | Leong, M.S. | |
dc.contributor.author | Choo, S.C. | |
dc.date.accessioned | 2014-06-17T06:55:48Z | |
dc.date.available | 2014-06-17T06:55:48Z | |
dc.date.issued | 1998-04-06 | |
dc.identifier.citation | Tan, L.S.,Leong, M.S.,Choo, S.C. (1998-04-06). Theory for the determination of backside contact resistance of semiconductor wafers from surface potential measurements. Solid-State Electronics 42 (4) : 589-594. ScholarBank@NUS Repository. | |
dc.identifier.issn | 00381101 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/62871 | |
dc.description.abstract | We present a method for the calculation of the potential on the surface of a homogeneous semiconductor slab with a disc source electrode on part of the front surface and a resistive contact over the backside of the entire slab. The imposed boundary condition of a constant potential over the source region gives rise to a pair of dual integral equations, which is transformed into a Fredholm integral equation of the second kind and subsequently solved using a simple numerical integration. The potential distributions on the surface of the slab are calculated for contact-to-semiconductor resistivity ratio in the range of 0 to 1 and for slab thickness ranging from 0.1 to 5x the radius of the disc contact. The results, which are directly applicable to the microelectronic test pattern NBS-3[1], show that there is a strong dependence of the surface potential distribution on the backside contact resistivity. A hitherto used two-dimensional model, with a strip source contact and restricted to the special case of a perfectly conducting backside contact, is shown to provide gross overestimates of the corresponding surface potentials when compared to the present method. © 1998 Elsevier Science Ltd. All rights reserved. | |
dc.source | Scopus | |
dc.type | Article | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.description.sourcetitle | Solid-State Electronics | |
dc.description.volume | 42 | |
dc.description.issue | 4 | |
dc.description.page | 589-594 | |
dc.description.coden | SSELA | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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