Steady state drain current technique for generation and recombination lifetime measurement in the SOI MOSFET

Abstract

A new steady state drain current technique is developed for both the generation and recombination lifetime extraction in the fully-depleted (FD) SOI MOSFET. At all times during the measurement, the device has one silicon surface maintained in strong accumulation, and the other surface in strong inversion. The accumulation layer is modulated with a negative ramp voltage applied to the gate, so that more holes are demanded by the accumulation layer (n-channel enhancement MOSFET). When the demand for the additional holes cannot be met by generation in the bulk of the silicon film, electrons from the inversion region have to be expelled, resulting in a decrease in the external drain current. The drain current saturates when the rate of demand for additional holes is balanced by the rate of hole generation. From the measured saturation drain current, together with the given ramp rate, the generation lifetime can be easily determined. A positive ramp voltage is used to extract recombination lifetime. As a non-pulse technique, only steady state parameters are measured. The technique has the added advantage of simplicity in the interpretation of the results.