Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/62379
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dc.titleLatent damage investigation on lateral nonuniform charge generation and stress-induced leakage current in silicon dioxide subjected to high-field current impulse stressing
dc.contributor.authorChim, W.-K.
dc.date.accessioned2014-06-17T06:50:24Z
dc.date.available2014-06-17T06:50:24Z
dc.date.issued2000
dc.identifier.citationChim, W.-K. (2000). Latent damage investigation on lateral nonuniform charge generation and stress-induced leakage current in silicon dioxide subjected to high-field current impulse stressing. IEEE Transactions on Electron Devices 47 (2) : 473-481. ScholarBank@NUS Repository.
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/62379
dc.description.abstractThis paper reports on positive lateral nonuniform (LNU) charge generation in silicon dioxide, and its relationship to transient or ac stress-induced leakage current (SILC), for MOS capacitor devices subjected to high-field current impulse stressing using a transmission line pulsing technique. The formation of LNU charge was attributed to the localized injection of avalanche hot carriers from the silicon substrate together with the accompanying impact ionization within the oxide. The short stress pulse duration was identified as an important factor for the generation of LNU charge as a longer duration stress pulse or dc stressing gives rise to more uniform charge trapping. A model, consisting of several similar area and equivalent MOS capacitors connected in parallel, was used to explain the effect of LNU charge generation on the high-frequency capacitance-voltage curves. Electrical annealing results indicate that the positive LNU charge traps are located close to the silicon-oxide interface. The LNU charges are distributed with a certain minimum trap energy level which require a critical fluence or gate voltage to be applied before significant LNU charge annealing is observed. The positive LNU charges, which lower the energy levels of neutral traps, are responsible for the transient SILC observed in the thicker oxide devices.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/16.822296
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume47
dc.description.issue2
dc.description.page473-481
dc.description.codenIETDA
dc.identifier.isiut000085344800032
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