Please use this identifier to cite or link to this item: https://doi.org/10.1109/7.892677
DC FieldValue
dc.titleDivisible load scheduling on single-level tree networks with buffer constraints
dc.contributor.authorLi, X.
dc.contributor.authorBharadwaj, V.
dc.contributor.authorKo, C.C.
dc.date.accessioned2014-06-17T06:46:58Z
dc.date.available2014-06-17T06:46:58Z
dc.date.issued2000-10
dc.identifier.citationLi, X.,Bharadwaj, V.,Ko, C.C. (2000-10). Divisible load scheduling on single-level tree networks with buffer constraints. IEEE Transactions on Aerospace and Electronic Systems 36 (4) : 1298-1308. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/7.892677" target="_blank">https://doi.org/10.1109/7.892677</a>
dc.identifier.issn00189251
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/62058
dc.description.abstractScheduling a divisible load on a heterogeneous single-level tree network with processors having finite-size buffers is addressed. We first present the closed-form solutions for the case when the available buffer size at each site is assumed to be infinite. Then we analyze the case when these buffer sizes are of finite size. For the first time in the domain of DLT (divisible load theory) literature, the problem of scheduling with finite-size buffers is addressed. For this case, we present a novel algorithm, referred to as incremental balancing strategy (IBS), to obtain an optimal load distribution. Algorithm IBS adopts a strategy to feed the divisible load in a step-by-step incremental balancing fashion by taking advantage of the available closed-form solutions of the optimal scheduling for the case without buffer size constraints. Based on the rigorous mathematical analysis, a number of interesting and useful properties exhibited by the algorithm are proven. We present a very useful discussion on the implications of this problem on the effect of sequencing discussed in the literature. Also, the impact of Rule A, a rule that obtains a reduced optimal network to achieve optimal processing time by eliminating a redundant set of processor-link pairs, is also discussed. Numerical examples are presented to ease understanding.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/7.892677
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.doi10.1109/7.892677
dc.description.sourcetitleIEEE Transactions on Aerospace and Electronic Systems
dc.description.volume36
dc.description.issue4
dc.description.page1298-1308
dc.description.codenIEARA
dc.identifier.isiutNOT_IN_WOS
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