Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/61928
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dc.titleCharacterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurements
dc.contributor.authorLing, C.H.
dc.contributor.authorYeow, Y.T.
dc.contributor.authorAh, L.K.
dc.date.accessioned2014-06-17T06:45:33Z
dc.date.available2014-06-17T06:45:33Z
dc.date.issued1992-11
dc.identifier.citationLing, C.H.,Yeow, Y.T.,Ah, L.K. (1992-11). Characterization of charge trapping in submicrometer NMOSFET's by gate capacitance measurements. Electron device letters 13 (11) : 587-589. ScholarBank@NUS Repository.
dc.identifier.issn01938576
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/61928
dc.description.abstractTrapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleElectron device letters
dc.description.volume13
dc.description.issue11
dc.description.page587-589
dc.description.codenEDLED
dc.identifier.isiutNOT_IN_WOS
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