Please use this identifier to cite or link to this item: https://doi.org/10.1049/el:20072620
DC FieldValue
dc.titleSPICE compatible modelling of on-chip coupled interconnects
dc.contributor.authorKumar, R.
dc.contributor.authorKang, K.
dc.contributor.authorRustagi, S.C.
dc.contributor.authorMouthaan, K.
dc.contributor.authorWong, T.K.S.
dc.date.accessioned2014-06-17T03:06:35Z
dc.date.available2014-06-17T03:06:35Z
dc.date.issued2007
dc.identifier.citationKumar, R., Kang, K., Rustagi, S.C., Mouthaan, K., Wong, T.K.S. (2007). SPICE compatible modelling of on-chip coupled interconnects. Electronics Letters 43 (24) : 1336-1338. ScholarBank@NUS Repository. https://doi.org/10.1049/el:20072620
dc.identifier.issn00135194
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/57474
dc.description.abstractOn-chip coupled interconnect lines are modelled using measured S-parameters. The physical consistency between single and coupled line model parameters are maintained in the proposed methodology. The SPICE compatible model is validated in both the frequency and the time domain using copper and ultra low-κ coupled interconnects.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1049/el:20072620
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1049/el:20072620
dc.description.sourcetitleElectronics Letters
dc.description.volume43
dc.description.issue24
dc.description.page1336-1338
dc.description.codenELLEA
dc.identifier.isiut000252184800010
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