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Title: Reconfigurable signal processing and hardware architecture for broadband wireless communications
Authors: Liang, Y.-C. 
Naveen, S.
Pilakkat, S.K.
Marath, A.K.
Keywords: Broadband communications
Cyclic prefix
Frequency-domain equalization
Reconfigurable signal processing
Software-defined radio
Issue Date: 1-Aug-2005
Citation: Liang, Y.-C.,Naveen, S.,Pilakkat, S.K.,Marath, A.K. (2005-08-01). Reconfigurable signal processing and hardware architecture for broadband wireless communications. Eurasip Journal on Wireless Communications and Networking 2005 (3) : 323-332. ScholarBank@NUS Repository.
Abstract: This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP) -based communication systems, including orthogonal frequency-division multiplexing (OFDM), single-carrier cyclic-prefix (SCCP) system, multicarrier (MC) code-division multiple access (MC-CDMA), MC direct-sequence CDMA (MC-DS-CDMA), CP-based CDMA (CP-CDMA), and CP-based direct-sequence CDMA (CP-DS-CDMA). A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.
Source Title: Eurasip Journal on Wireless Communications and Networking
ISSN: 16871472
DOI: 10.1155/WCN.2005.323
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