Please use this identifier to cite or link to this item: https://doi.org/10.1109/16.902743
Title: Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET
Authors: Cheng, Z.-Y. 
Ling, C.H. 
Issue Date: Feb-2001
Citation: Cheng, Z.-Y., Ling, C.H. (2001-02). Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET. IEEE Transactions on Electron Devices 48 (2) : 388-391. ScholarBank@NUS Repository. https://doi.org/10.1109/16.902743
Abstract: A gate-channel capacitance minimum occurs in the capacitance-voltage (C-V) curve of a fully-depleted SOI MOSFET, when the front silicon surface is biased into accumulation while the back surface is maintained in strong inversion. This observation is explained in terms of a model based on the depletion width of the silicon film, taking into account the small accumulation and inversion layer thickness. A simple method is proposed to determine the flat-band potential in the SOI MOSFET.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/56114
ISSN: 00189383
DOI: 10.1109/16.902743
Appears in Collections:Staff Publications

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