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|Title:||CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications||Authors:||Shabbir, A.
|Keywords:||Automated design flow
|Issue Date:||Jul-2010||Citation:||Shabbir, A., Kumar, A., Stuijk, S., Mesman, B., Corporaal, H. (2010-07). CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications. Journal of Systems Architecture 56 (7) : 265-277. ScholarBank@NUS Repository. https://doi.org/10.1016/j.sysarc.2010.03.007||Abstract:||Future embedded systems demand multi-processor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semi-automated, time consuming and error prone. In this paper, we present a fully automated design flow to generate communication assist (CA) based multi-processor systems (CA-MPSoC). A worst-case performance model of our CA is proposed so that the performance of the CA-based platform can be analyzed before its implementation. The design flow provides performance estimates and timing guarantees for both hard real-time and soft real-time applications, provided the task to processor mappings are given by the user. The flow automatically generates a super-set hardware that can be used in all use-cases of the applications. The software for each of these use-cases is also generated including the configuration of communication architecture and interfacing with application tasks. CA-MPSoC has been implemented on Xilinx FPGAs for evaluation. Further, it is made available on-line for the benefit of the research community and in this paper, it is used for performance analysis of two real life applications, Sobel and JPEG encoder executing concurrently. The CA-based platform generated by our design flow records a maximum error of 3.4% between analyzed and measured periods. Our tool can also merge use-cases to generate a super-set hardware which accelerates the evaluation of these use-cases. In a case study with six applications, the use-case merging results in a speed up of 18 when compared to the case where each use-case is evaluated individually. © 2010 Elsevier B.V. All rights reserved.||Source Title:||Journal of Systems Architecture||URI:||http://scholarbank.nus.edu.sg/handle/10635/55248||ISSN:||13837621||DOI:||10.1016/j.sysarc.2010.03.007|
|Appears in Collections:||Staff Publications|
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