Please use this identifier to cite or link to this item: https://doi.org/10.1109/JSSC.2011.2177178
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dc.titleA pulse shaping technique for spur suppression in injection-locked synthesizers
dc.contributor.authorIzad, M.M.
dc.contributor.authorHeng, C.-H.
dc.date.accessioned2014-06-16T09:34:23Z
dc.date.available2014-06-16T09:34:23Z
dc.date.issued2012-02
dc.identifier.citationIzad, M.M., Heng, C.-H. (2012-02). A pulse shaping technique for spur suppression in injection-locked synthesizers. IEEE Journal of Solid-State Circuits 47 (3) : 652-664. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2011.2177178
dc.identifier.issn00189200
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/54747
dc.description.abstractFrequency synthesizers based on sub-harmonic injection- locked oscillators can reduce power and area effectively. However, they suffer from unwanted side-bands caused by undesirable harmonics in the injection pulse. This paper presents a pulse shaping technique that reduces these undesirable harmonics in the injection pulse and produces low-spur synthesized output. The robustness of the proposed technique and the impact of circuit non-idealities are also discussed in depth. A test chip tailored to the first band group of WiMedia UWB is fabricated in 0.13- m CMOS technology to verify the effectiveness of this technique. Experimental results show that the proposed pulse shaping attenuates the spurs by 22 dB and suppresses them below 47 dBc. The prototype achieves a switching time of less than 4.7 ns and phase noise of 122 dBc/Hz@1 MHz offset at 4.488 GHz. The chip occupies an active area of 0.15 mm and draws only 18 mA from a 1.2-V supply. © 2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/JSSC.2011.2177178
dc.sourceScopus
dc.subjectInjection-locked oscillator (ILO)
dc.subjectPulse shaping
dc.subjectSpur suppression
dc.subjectSub-harmonic injection locking
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/JSSC.2011.2177178
dc.description.sourcetitleIEEE Journal of Solid-State Circuits
dc.description.volume47
dc.description.issue3
dc.description.page652-664
dc.description.codenIJSCB
dc.identifier.isiut000300577500006
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