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|Title:||A 0.7-V 17.4-μ W 3-lead wireless ECG SoC||Authors:||Khayatzadeh, M.
|Issue Date:||2013||Citation:||Khayatzadeh, M., Zhang, X., Tan, J., Liew, W.-S., Lian, Y. (2013). A 0.7-V 17.4-μ W 3-lead wireless ECG SoC. IEEE Transactions on Biomedical Circuits and Systems 7 (5) : 583-592. ScholarBank@NUS Repository. https://doi.org/10.1109/TBCAS.2013.2279398||Abstract:||This paper presents a fully integrated sub-1 V 3-lead wireless ECG System-on-Chip (SoC) for wireless body sensor network applications. The SoC includes a two-channel ECG front-end with a driven-right-leg circuit, an 8-bit SAR ADC, a custom-designed 16-bit microcontroller, two banks of 16 kb SRAM, and a MICS band transceiver. The microcontroller and SRAM blocks are able to operate at sub-/near-threshold regime for the best energy consumption. The proposed SoC has been implemented in a standard 0.13-μm CMOS process. Measurement results show the microcontroller consumes only 2.62 pJ per instruction at 0.35 V. Both microcontroller and memory blocks are functional down to 0.25 V. The entire SoC is capable of working at single 0.7-V supply. At the best case, it consumes 17.4 μ W in heart rate detection mode and 74.8 μ W in raw data acquisition mode under sampling rate of 500 Hz. This makes it one of the best ECG SoCs among state-of-the-art biomedical chips. © 2007-2012 IEEE.||Source Title:||IEEE Transactions on Biomedical Circuits and Systems||URI:||http://scholarbank.nus.edu.sg/handle/10635/53880||ISSN:||19324545||DOI:||10.1109/TBCAS.2013.2279398|
|Appears in Collections:||Staff Publications|
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