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|Title:||A 0.5-V 35-μ W 85-dB DR double-sampled δσ modulator for audio applications||Authors:||Yang, Z.
Global-loop CMFB circuit
|Issue Date:||Feb-2012||Citation:||Yang, Z., Yao, L., Lian, Y. (2012-02). A 0.5-V 35-μ W 85-dB DR double-sampled δσ modulator for audio applications. IEEE Journal of Solid-State Circuits 47 (3) : 722-735. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2011.2181677||Abstract:||This paper presents a 0.5-V 1.5-bit double-sampled δσ modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled δσ modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13-μm CMOS technology with a core area of 0.57 mm . The measured results show that when operating from a 0.5-V supply and clocked at 1.25 MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2 μW for a 20-kHz signal bandwidth. © 2012 IEEE.||Source Title:||IEEE Journal of Solid-State Circuits||URI:||http://scholarbank.nus.edu.sg/handle/10635/53879||ISSN:||00189200||DOI:||10.1109/JSSC.2011.2181677|
|Appears in Collections:||Staff Publications|
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