Please use this identifier to cite or link to this item: https://doi.org/10.1109/JSSC.2012.2216704
DC FieldValue
dc.title3-5 GHz 4-channel UWB beamforming transmitter with 1° scanning resolution through calibrated vernier delay line in 0.13-μm CMOS
dc.contributor.authorWang, L.
dc.contributor.authorLian, Y.
dc.contributor.authorHeng, C.-H.
dc.date.accessioned2014-06-16T09:22:44Z
dc.date.available2014-06-16T09:22:44Z
dc.date.issued2012
dc.identifier.citationWang, L., Lian, Y., Heng, C.-H. (2012). 3-5 GHz 4-channel UWB beamforming transmitter with 1° scanning resolution through calibrated vernier delay line in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits 47 (12) : 3145-3159. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2012.2216704
dc.identifier.issn00189200
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/53855
dc.description.abstractA 3-5 GHz 4-channel UWB beamforming transmitter with 1° scanning resolution and 135° scanning range is presented in this paper. The fine resolution is attained through Vernier delay lines capable of fine resolution down to 10 ps. Accurate path delay across channels as well as UWB pulse center frequency are achieved through the proposed Δσ DLL calibration technique, which speeds up the calibration by 48 times compared with a counter-based approach. A novel power spectral density calibration circuit is included to adjust the UWB pulse shape for meeting the FCC mask. Fabricated in 0.13-μm CMOS, the proposed transmitter occupies only 7.2 μm. The power consumption is 9.6 mW while transmitting at 80 Mbps, with each transmitter achieving 10 pJ/bit and transmitter efficiency of 7.5%. This is about ten times better than those existing UWB beamforming transmitters. © 2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/JSSC.2012.2216704
dc.sourceScopus
dc.subjectΔσ DLL
dc.subjectAll-digital UWB transmitter
dc.subjectbeamforming delay chain
dc.subjectPSD calibration circuit
dc.subjectUWB beamforming transmitter
dc.subjectVernier delay line
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.departmentPHYSICS
dc.description.doi10.1109/JSSC.2012.2216704
dc.description.sourcetitleIEEE Journal of Solid-State Circuits
dc.description.volume47
dc.description.issue12
dc.description.page3145-3159
dc.description.codenIJSCB
dc.identifier.isiut000312829900024
Appears in Collections:Staff Publications

Show simple item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

21
checked on Oct 17, 2019

WEB OF SCIENCETM
Citations

15
checked on Oct 17, 2019

Page view(s)

130
checked on Oct 13, 2019

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.