Please use this identifier to cite or link to this item:
|Title:||Performance spread optimization of MOS VLSI circuit by statistical parameter design||Authors:||Chen, H.M.
|Issue Date:||1999||Citation:||Chen, H.M.,Samudra, G.S.,Chan, D.S.H.,Ibrahim, Y. (1999). Performance spread optimization of MOS VLSI circuit by statistical parameter design. International Symposium on IC Technology, Systems and Applications 8 : 64-67. ScholarBank@NUS Repository.||Abstract:||The circuit performance and the parametric yield are important for VLSI design, but it is not enough to consider only these factors. One of the other significant factors is the performance spread which should be as smali as possible. Due to the manufacturing process variation, the circuit performance has some variations around its nominal performance. In order to decrease this performance spread efficiently, a novel algorithm based on the steepest-descent method and some statistical methods is introduced. At first, a linear relationship is assumed between the parameter values and the circuit performance, and then only tens of simulations need to be run to identify coefficients in the performance expression. In order to save the cost, novel analytical means are used to calculate the performance spread and its gradient. This algorithm decreases the spread efficiently and one example is shown to demonstrate its capability.||Source Title:||International Symposium on IC Technology, Systems and Applications||URI:||http://scholarbank.nus.edu.sg/handle/10635/50638|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Apr 19, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.