Please use this identifier to cite or link to this item:
|Title:||Yield optimization by design centering & worst-case distance analysis||Authors:||Samudra, G.S.
|Issue Date:||1999||Citation:||Samudra, G.S.,Chen, H.M.,Chan, D.S.H.,Ibrahim, Yaacob (1999). Yield optimization by design centering & worst-case distance analysis. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors : 289-290. ScholarBank@NUS Repository.||Abstract:||Process variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it is a preferred method as it directly translates into profits. This paper presents an efficient and novel method to improve the VLSI parametric yield by selecting optimum parameter values. This method utilizes the Worst-Case Distance Analysis, Design Centering and Gradient-Dependent techniques. One circuit example is presented to demonstrate the optimization scheme.||Source Title:||Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors||URI:||http://scholarbank.nus.edu.sg/handle/10635/50611|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Apr 19, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.