Instruction Cache Optimizations in Embedded Real-Time Systems

Abstract

Caches are widely employed in modern embedded real-time systems. They bridge the performance gap between the fast CPU and the slow off-chip memory. However, they also introduce timing unpredictability in real-time systems. Existing approaches dealing with timing unpredictability of caches usually employ static cache analysis or full cache locking techniques. However, static cache analysis may produce inaccurate results, while full cache locking may have negative impact on the overall execution time. In this thesis, we propose partial cache locking technique to optimize the worst-case performance of embedded real-time systems. We studies partial instruction cache locking in the context of different architectures and system models in embedded real-time systems. The worst-case performance of the applications is greatly improved, compared to the existing approaches.