Please use this identifier to cite or link to this item:
|Title:||Formal modeling and validation of Stateflow diagrams||Authors:||Chen, C.
|Issue Date:||2012||Citation:||Chen, C.,Sun, J.,Liu, Y.,Dong, J.S.,Zheng, M. (2012). Formal modeling and validation of Stateflow diagrams. International Journal on Software Tools for Technology Transfer 14 (6) : 653-671. ScholarBank@NUS Repository. https://doi.org/10.1007/s10009-012-0235-0||Abstract:||Stateflow is an industrial tool for modeling and simulating control systems in model-based development. In this paper, we present our latest work on automatic verification of Stateflow using model-checking techniques. We propose an approach to systematically translate Stateflow diagrams to a formal modeling language called CSP# by precisely following Stateflow's execution semantics, which is described by examples. A translator is developed inside the Process Analysis Toolkit (PAT) model checker to automate this process with the support of various Stateflow advanced modeling features. Formal analysis can be conducted on the transformed CSP# with PAT's simulation and model-checking power. Using our approach, we can not only detect bugs in Stateflow diagrams, but also discover subtle semantics flaws in Stateflow user's guide and demo cases. © 2012 Springer-Verlag.||Source Title:||International Journal on Software Tools for Technology Transfer||URI:||http://scholarbank.nus.edu.sg/handle/10635/43028||ISSN:||14332779||DOI:||10.1007/s10009-012-0235-0|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Oct 19, 2019
checked on Oct 14, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.