Design space exploration of caches using compressed traces

Abstract

Memory subsystem, in particular, cache design is important for both high performance and embedded computing systems. The trend towards increased customization for embedded systems, in addition, requires the design of an optimal cache configuration for each application. Trace driven simulation is widely used to evaluate cache performance. However, traces are storage inefficient and simulation is too slow especially when hundreds of design points need to be evaluated. Trace based simulation has two sources of redundancies: multiple occurrences of the same sequence in the trace and containment relationship among cache configurations. We exploit both the redundancies in a unified manner by simulating multiple cache configurations in a single pass directly over a compressed trace (which has already identified the repetitive sequences). Experimental results indicate that our approach achieves significant savings both in storage and in simulation time compared to existing methods.