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|Title:||Integrated scratchpad memory optimization and task scheduling for MPSoC architectures||Authors:||Suhendra, V.
|Issue Date:||2006||Citation:||Suhendra, V.,Raghavan, C.,Mitra, T. (2006). Integrated scratchpad memory optimization and task scheduling for MPSoC architectures. CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems : 401-410. ScholarBank@NUS Repository. https://doi.org/10.1145/1176760.1176809||Abstract:||Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a complex electronic system. An MPSoC architecture is, in general, customized for an embedded application. A critical component of this customization process is the on-chip memory system configuration. Embedded systems increasingly employ software-controlled scratchpad memory(SPM) due to its inherent advantages in terms of area, energy, and timing predictability compared to caches. An application-specific flexible partitioning of the on-chip SPM budget among the processors is critical for performance optimization. Moreover, scheduling the tasks of an application on to the processors and partitioning the SPM are inter-dependent even though these steps are decoupled in the traditional design space exploration process. In this work, we design an integrated task mapping, scheduling, SPM partitioning, and data allocation technique based on Integer Linear Programming(ILP)formulation. Our ILP formulation explores the optimal performance limit and shows that integrated task schedul-ing and SPM optimization improves performance by up to 80% for embedded applications. Copyright 2006 ACM.||Source Title:||CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems||URI:||http://scholarbank.nus.edu.sg/handle/10635/41779||ISBN:||1595935436||DOI:||10.1145/1176760.1176809|
|Appears in Collections:||Staff Publications|
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