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|Title:||Efficient custom instructions generation for system-level design||Authors:||Huynh, H.P.
|Issue Date:||2010||Citation:||Huynh, H.P.,Liang, Y.,Mitra, T. (2010). Efficient custom instructions generation for system-level design. Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 : 445-448. ScholarBank@NUS Repository. https://doi.org/10.1109/FPT.2010.5681456||Abstract:||Customizable embedded processors, where the processor core can be enhanced with application-specific instructions, can provide high performance similar to custom design circuits with the flexibility of software solutions. The acceptability of customizable processors, however, critically hinges on the availability of design automation tools that can identify high-quality custom instructions from the software specification of an application. Automated customization has enjoyed significant research and commercial progress in the recent past. However, this process is currently not closely coupled with the overall system-level design flow. We propose an iterative solution that enables rapid feedback between the custom instructions generation and the system-level design decision. A key component of our solution is an efficient algorithm inspired by multi-level graph partitioning that can quickly produce high-quality custom instructions for the critical regions and thereby alleviate the system performance bottleneck. © 2010 IEEE.||Source Title:||Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10||URI:||http://scholarbank.nus.edu.sg/handle/10635/41757||ISBN:||9781424489817||DOI:||10.1109/FPT.2010.5681456|
|Appears in Collections:||Staff Publications|
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