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https://scholarbank.nus.edu.sg/handle/10635/41590
DC Field | Value | |
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dc.title | Systematic debugging of real-time systems based on incremental satisfiability counting | |
dc.contributor.author | Andrei, Ş. | |
dc.contributor.author | Chin, W.-N. | |
dc.contributor.author | Cheng, A.M.K. | |
dc.contributor.author | Lupu, M. | |
dc.date.accessioned | 2013-07-04T08:31:05Z | |
dc.date.available | 2013-07-04T08:31:05Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | Andrei, Ş.,Chin, W.-N.,Cheng, A.M.K.,Lupu, M. (2005). Systematic debugging of real-time systems based on incremental satisfiability counting. Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS : 519-528. ScholarBank@NUS Repository. | |
dc.identifier.issn | 15453421 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/41590 | |
dc.description.abstract | Real-time logic (RTL) [1, 2, 3] is useful for the verification of a safety assertion with respect to the specification of a real-time system. Since the satisfiability problem for RTL is undecidable, the systematic debugging of a real-time system appears impossible. This paper provides a first step towards this challenge. With RTL, each propositional formula corresponds to a verification condition. The number of truth assignments of a propositional formula helps to determine the timing constraints which should be added or modified to the system's specification. We have implemented a tool (called SDRTL, [4]) that is able to perform systematic debugging. The confidence of our approach is high as we have evaluated SDRTL on several existing industrial-based applications. © 2005 IEEE. | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | COMPUTER SCIENCE | |
dc.description.sourcetitle | Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS | |
dc.description.page | 519-528 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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