Please use this identifier to cite or link to this item:
https://doi.org/10.1109/RTAS.2006.22
DC Field | Value | |
---|---|---|
dc.title | Interactive schedulability analysis | |
dc.contributor.author | Bordoloi, U.D. | |
dc.contributor.author | Chakraborty, S. | |
dc.date.accessioned | 2013-07-04T08:15:22Z | |
dc.date.available | 2013-07-04T08:15:22Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | Bordoloi, U.D.,Chakraborty, S. (2006). Interactive schedulability analysis. Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2006 : 147-156. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/RTAS.2006.22" target="_blank">https://doi.org/10.1109/RTAS.2006.22</a> | |
dc.identifier.isbn | 0769525164 | |
dc.identifier.issn | 15453421 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/40917 | |
dc.description.abstract | A typical design process for real-time embedded systems involves choosing the values of certain system parameters and performing a schedulability analysis to determine whether all deadline constraints can be satisfied. If such an analysis returns a negative answer, then some of the parameters are modified and the analysis is invoked once again. This iteration is repeated till a schedulable design is obtained. However, the schedulability analysis problem for most task models is intractable (usually co-NP hard) and hence such an iterative design process is often very expensive. To get around this problem, we introduce the concept of "interactive" schedulability analysis. It is based on the observation that if only a small number of system parameters are changed, then it is not necessary to rerun the full schedulability analysis algorithm, thereby making the iterative design process considerably faster. We refer to this analysis as being "interactive" because it is supposed to be run in an interactive mode. This concept is fairly general and can be applied to a wide variety of task models. In this paper we have chosen the recurring real-time task model because it can be used to represent realistic applications from the embedded systems domain (containing conditional branches and fine-grained deadline constraints). Our experimental results show that using our scheme can lead to more than 20 x speedup for each invocation of the schedulability analysis algorithm, compared to the case where the full algorithm is run. © 2006 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/RTAS.2006.22 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | COMPUTER SCIENCE | |
dc.description.doi | 10.1109/RTAS.2006.22 | |
dc.description.sourcetitle | Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS | |
dc.description.volume | 2006 | |
dc.description.page | 147-156 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
Show simple item record
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.