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|Title:||Cache modeling in probabilistic execution time analysis||Authors:||Liang, Y.
|Issue Date:||2008||Citation:||Liang, Y.,Mitra, T. (2008). Cache modeling in probabilistic execution time analysis. Proceedings - Design Automation Conference : 319-324. ScholarBank@NUS Repository. https://doi.org/10.1109/DAC.2008.4555831||Abstract:||Probabilistic Execution Time Analysis, Cache Modeling. Multimedia-dominated consumer electronics devices (such as cellular phone, digital camera, etc.) operate under soft real-time constraints. Overly pessimistic worst-case execution time analysis techniques borrowed from hard real-time systems domain are not particularly suitable in this context. Instead, the execution time distribution of a task provides a more valuable input to the system-level performance analysis frameworks. Both program inputs and underlying architecture contribute to the execution time variation of a task. But existing probabilistic execution time analysis approaches mostly ignore architectural modeling. In this paper, we take the first step towards remedying this situation through instruction cache modeling. We introduce the notion of probabilistic cache states to model the evolution of cache content during program execution over multiple inputs. In particular, we estimate the mean and variance of execution time of a program across inputs in the presence of instruction cache. The experimental evaluation confirms the scalability and accuracy of our probabilistic cache modeling approach. Copyright 2008 ACM.||Source Title:||Proceedings - Design Automation Conference||URI:||http://scholarbank.nus.edu.sg/handle/10635/40773||ISBN:||9781605581156||ISSN:||0738100X||DOI:||10.1109/DAC.2008.4555831|
|Appears in Collections:||Staff Publications|
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