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|Title:||Power management of interactive 3D games using frame structures||Authors:||Gu, Y.
|Issue Date:||2008||Citation:||Gu, Y., Chakraborty, S. (2008). Power management of interactive 3D games using frame structures. Proceedings of the IEEE International Frequency Control Symposium and Exposition : 679-684. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSI.2008.102||Abstract:||We propose a novel dynamic voltage scaling (DVS) scheme that is specifically directed towards 3D graphics-intensive interactive game applications running on battery-operated portable devices. The key to this DVS scheme lies in parsing each game frame to estimate its rendering workload and then using such an estimate to scale the voltage/frequency of the underlying processor. The main novelty of this scheme stems from the fact that game frames offer a rich variety of "structural" information (e.g. number of brush and alias models, texture information and light maps) which can be exploited to estimate their processing workload. Although DVS has been extensively applied to video decoding applications, compressed video frames do not offer any information (beyond the frame types - I, B or P) that can be used in a similar manner to estimate their processing workload. As a result, DVS algorithms designed for video decoding mostly rely on control-theoretic feedback mechanisms, where the workload of a frame is predicted from the workloads of the previously-rendered frames. We show that compared to such history-based predictors, our proposed scheme performs significantly better for game applications. Our experimental results, based on the Quake II game engine running on Windows XP, show that for the same energy consumption our scheme results in more than 50% improvement in quality (measured in terms of number of frames meeting their deadlines) compared to history-based prediction schemes. © 2008 IEEE.||Source Title:||Proceedings of the IEEE International Frequency Control Symposium and Exposition||URI:||http://scholarbank.nus.edu.sg/handle/10635/40682||ISBN:||0769530834||DOI:||10.1109/VLSI.2008.102|
|Appears in Collections:||Staff Publications|
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