Please use this identifier to cite or link to this item:
|Title:||Intra- and inter-processor hybrid performance modeling for MPSoC architectures||Authors:||Ophelders, F.E.B.
|Issue Date:||2008||Citation:||Ophelders, F.E.B.,Chakraborty, S.,Corporaal, H. (2008). Intra- and inter-processor hybrid performance modeling for MPSoC architectures. Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008 : 91-96. ScholarBank@NUS Repository. https://doi.org/10.1145/1450135.1450156||Abstract:||The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance model-ing techniques. Here, the idea is to apply different modeling and analysis techniques to different subsystems/components of an ar-chitecture/application. Such hybrid techniques often turn out to be more efficient and accurate compared to relying on a single analy-sis technique for the entire system. However, the challenge asso-ciated with this approach is to combine the different analysis re-sults effectively to obtain conservative performance estimates for the entire system. In this paper we study a hybrid scheme where certain system components are simulated (e.g. using instruction set simulators), whereas others are analyzed using a formal tech-nique called Real-Time Calculus (RTC). The main novelty of our approach stems from our use of this hybrid technique even for mul-tiple tasks mapped onto a single processing element. In contrast to this, previous approaches relied on either full simulation or RTC-based analysis for an entire architectural component (e.g. a proces-sor or a bus). The techniques we develop in this paper therefore al-low for both intra- and inter-processor hybrid performance model-ing and show how the different analysis results can be combined to efficiently obtain tight performance estimates for complex MPSoC architectures. We demonstrate the usefulness of this approach us-ing an MPEG-2 decoder application that is partitioned and mapped onto two processing elements connected by FIFO buffers. Copyright 2008 ACM.||Source Title:||Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008||URI:||http://scholarbank.nus.edu.sg/handle/10635/40672||ISBN:||9781605584706||DOI:||10.1145/1450135.1450156|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Aug 18, 2019
checked on Aug 19, 2019
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.