Please use this identifier to cite or link to this item:
|Title:||A unified WCET analysis framework for multi-core platforms||Authors:||Chattopadhyay, S.
|Issue Date:||2012||Citation:||Chattopadhyay, S., Kee, C.L., Roychoudhury, A., Kelter, T., Marwedel, P., Falk, H. (2012). A unified WCET analysis framework for multi-core platforms. Real-Time Technology and Applications - Proceedings : 99-108. ScholarBank@NUS Repository. https://doi.org/10.1109/RTAS.2012.26||Abstract:||With the advent of multi-core architectures, worst case execution time (WCET) analysis has become an increasingly difficult problem. In this paper, we propose a unified WCET analysis framework for multi-core processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multi-core architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs. © 2012 IEEE.||Source Title:||Real-Time Technology and Applications - Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/40443||ISBN:||9780769546674||ISSN:||10801812||DOI:||10.1109/RTAS.2012.26|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Jul 9, 2020
WEB OF SCIENCETM
checked on Jul 1, 2020
checked on Jun 29, 2020
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.