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|Title:||Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor||Authors:||Wang, H.-C.
|Issue Date:||2006||Citation:||Wang, H.-C.,Yuen, C.-K. (2006). Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor. 20th International Parallel and Distributed Processing Symposium, IPDPS 2006 2006. ScholarBank@NUS Repository. https://doi.org/10.1109/IPDPS.2006.1639289||Abstract:||To design a Java processor with traditional modern processor architecture, the Instruction Level Parallelism (ILP) is not readily exploitable due to stack operands dependencies. This paper presents a dataflow-based instruction tagging scheme. With instruction tagging, the independent bytecode instruction groups with stack dependences are identified. The different bytecode instruction group can be executed in parallel because there are no stack dependences among them. With the instruction tagging scheme, we propose a tag-based multi-issue semi-in-order (TMSI) Java processor. The processor takes advantage of instruction-tagging and stack-folding to generate the tagged register-based instructions. When the tagged instructions are ready, they are bundled out-of-order depending on data availability to form VLIW-like instruction words and issued in-order. To achieve high performance, a VLIW engine is employed. We have conducted some experiments in our TMSI simulation environment using SPECjvm98 and Linpack workload. The results indicate that the proposed processor has good performance gain. © 2006 IEEE.||Source Title:||20th International Parallel and Distributed Processing Symposium, IPDPS 2006||URI:||http://scholarbank.nus.edu.sg/handle/10635/40094||ISBN:||1424400546||DOI:||10.1109/IPDPS.2006.1639289|
|Appears in Collections:||Staff Publications|
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