Schottky Barrier Engineering for Contacts in Advanced CMOS Technology

Abstract

High parasitic Source/Drain (S/D) series resistance is a bottleneck for achieving high drive current for Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs) at 22 nm technology node and beyond. A major contribution of the S/D series resistance is the contact resistance (Rc) at the metal/semiconductor interface. Reducing the effective Schottky barrier height at this interface would reduce Rc. In this thesis, four different contact engineering techniques were explored to modulate the effective electron Schottky barrier height on silicon (Si), silicon-carbon (Si:C), and germanium (Ge) S/D materials. They were (1) ammonium sulfide chemical treatment of Si before nickel silicide contact formation, (2) deposition of a dysprosium layer on Si before nickel silicide contact formation, (3) nickel silicide contact formation on Si:C substrates with different substitutional carbon concentration, and (4) laser anneal of nickel on Ge. This thesis research provides potential contact technology options for CMOS devices in sub-20 nm technology nodes.