Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/32753
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dc.titleMethod of fabricating a CMOS device with dual metal gate electrodes
dc.contributor.authorPARK, CHANG SEO
dc.contributor.authorCHO, BYUNG JIN
dc.contributor.authorBALASUBRAMANIAN, NARAYANAN T.
dc.date.accessioned2012-05-02T02:29:53Z
dc.date.available2012-05-02T02:29:53Z
dc.date.issued2008-01-08
dc.identifier.citationPARK, CHANG SEO,CHO, BYUNG JIN,BALASUBRAMANIAN, NARAYANAN T. (2008-01-08). Method of fabricating a CMOS device with dual metal gate electrodes. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/32753
dc.description.abstractA method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AIN.sub.x) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US7316950
dc.sourcePatSnap
dc.typePatent
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.identifier.isiutNOT_IN_WOS
dc.description.patentnoUS7316950
dc.description.patenttypeGranted Patent
dc.contributor.patentassigneeNATIONAL UNIVERSITY OF SINGAPORE
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