Vertical Silicon Nanowire Gate-All-Around Tunneling Field Effect Tranistors for Future Low Power Nanoelectronics

Abstract

Scaling of MOSFET to improve device performance and increase device density faces enormous challenges beyond the 22 nm node due to excessive increase in passive power. This arises due to the non scalability of the subthreshold swing (SS) that also limits further reduction in MOSFET threshold voltage, Vth and hence supply voltage, Vdd. To overcome this problem and to design more energy-efficient devices, alternative transistor designs with low SS are needed. One of such devices is the TFET. Unlike the MOSFET, which utilizes thermionic injection of carriers, TFET uses tunneling as the carrier injection mechanism. Therefore, it?s possible for TFET to achieve low OFF state current as well as SS below the theoretical limit of 60mV/decade for MOSFETs at room temperature. In this work, we present vertical silicon nanowire (SiNW) gate-all-around (GAA) p-TFET and n-TFET devices with low SS of 30mV/decade. An abrupt source-side doping gradient achieved by dopant segregation through nickel silicidation is the key step to achieve these low SS. Vertical SiNW-GAA structures also provides excellent gate electrostatic control, high integration density for circuit functionality and compatibility with existing CMOS technology.