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Title: Development of high mobility channel layer formation technology for high speed CMOS Devices
Keywords: high mobility, III-V MOSFET, GaAs-OI, Ge condensation, PH3 treatment, phosphorus nitride
Issue Date: 18-Oct-2010
Citation: OH HOON JUNG (2010-10-18). Development of high mobility channel layer formation technology for high speed CMOS Devices. ScholarBank@NUS Repository.
Abstract: As the gate length of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) approaches ~10 nm regime, the traditional Si CMOS scaling faces its fundamental limits. Among the proposed technical solutions, GaAs-based III-V compound semiconductors are actively being studied as a possible alternative for a high speed n-channel MOSFET (NMOSFET) due to their low effective electron masses, high electron mobilities, the accumulated knowledge, and the difficulty in Ge NMOSFET realization. However, the III-V MOSFET technology should address several critical issues with the device realization. The challenges include how to integrate a high quality III-V channel layer into Si platform and how to achieve the thermally stable III-V/high-k interface without Fermi level pinning. In the first part of this thesis, novel approaches for GaAs-on-insulator (GaAs-OI) fabrication technology were explored to overcome the physical and technical challenges in growing the GaAs heteroepitaxial layer in Si platform. The cost-effective Ge-condensation technique was developed to provide a compositionally graded SiGe-on-insulator (SGOI) as a virtual substrate for the GaAs heteroepitaxy on Silicon-on-insulator (SOI). A modified two-step Ge-condensation resulted in 42 nm thick SGOI with 71 % Ge concentration on top of the SGOI with an excellent crystalline quality. For the first time, a device quality GaAs-OI structure has been realized on a Si wafer through the graded SGOI virtual substrate using molecular beam epitaxy with introduction of migration-enhanced epitaxy technique. In the second part of this thesis, fabrication processes were developed to realize the NMOSFET integrated with metal-organic chemical vapor deposited (MOCVD) Hf-based high-k/metal gate stack on a GaAs-based III-V channel in a self-aligned gate-first fabrication scheme. The main process steps included pre-deposition cleaning, HfO2 and HfAlO MOCVDs, and Si implanted n+ S/D formation processes. The focus was on improving III-V/high-k interface quality to mitigate Fermi level pinning issue. Electrical properties were investigated to optimize the material combinations and processes further. Consequently, enhancement mode NMOSFET with ~3 times higher peak mobility over the universal mobility of Si has been demonstrated with MOCVD HfAlO/TaN gate stack on In0.53Ga0.47As channel. Finally, a Si-compatible passivation technique using in situ PH3 treatment is proposed, explored and investigated to improve the InGaAs NMOSFET performance. It was found that at low pressure PH3-N2 plasma condition, a 1 monolayer thick phosphorus nitride (PxNy) layer is formed with an underlying P-for-As exchanged layer as a minor product on InGaAs substrate in a wide range of process window. The improved interface quality of the PxNy-passivated In0.53Ga0.47As is identified and compared with the non-passivated InGaAs and PH3-based passivated InGaAs without PxNy layer with chemical and physical properties. The PxNy passivation greatly improved electrical properties of the InGaAs MOSFET devices. Technology demonstration with this novel PxNy passivation achieved the low subthreshold slope approaching the ideal value of 60 mV/dec as well as the significantly enhanced peak mobility in the inversion layer of ~5 times the universal Si mobility at the corresponding low field. Thermal stability of the PxNy-passivated interface was examined up to 750 oC with the self-aligned InGaAs/HfO2 MOSFET devices by activating the S/D at different temperatures.
Appears in Collections:Ph.D Theses (Open)

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