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|Title:||Top-down engineered silicon and germanium nanowire MOSFET||Authors:||PENG JIANWEI||Keywords:||Silicon, Germanium, Nanowire, MOSFET, Top-Down, Core/Shell||Issue Date:||19-Aug-2010||Citation:||PENG JIANWEI (2010-08-19). Top-down engineered silicon and germanium nanowire MOSFET. ScholarBank@NUS Repository.||Abstract:||A large part of the success of integrated circuits could be attributed to the continuous scaling of metal-oxide-semiconductor-field effect-transistors (MOSFETs), which lead to faster and cheaper transistors simultaneously. However, as the transistor dimensions shrink down to the sub-100 nm regime, it has become challenging to continuously improve transistors? performance by conventional scaling techniques. It is found that on-state current, power consumption and short channel effects have a tradeoff relationship with each others. As a result, any technique to improve transistor performance needs to overcome/mitigate the stringent constrains of this tradeoff. The nanowire transistor architecture and germanium (Ge) channel are considered to be promising performance boosters to improve transistor performance which can effectively overcome/mitigate the tradeoff between on-state current, power consumption and short channel effects. In this thesis, nanowire gate-all-around (GAA) Schottky Barrier (SB)-MOSFETs and Ge nanowire transistors are studied as potential candidates for future high performance transistor applications. Nanowire GAA MOSFETs integrated with 1-D NiSi Schottky source/drain (S/D) were explored and demonstrated on silicon (Si) nanowires with diameter down to 4 nm. Although NiSi has a high hole SB height of 0.46 eV, the Si nanowire SB-MOSFET still demonstrated a high on-state current and a subthreshold swing (SS) close to the ideal value 60 mV/dec. The performance improvement was attributed to the improved carrier injection as a result of the superior gate electrostatic control over the channel in the GAA nanowire device architecture. As a potential performance booster, Ge nanowire transistors were explored. Ge nanowires (NWs) were fabricated on an epitaxial grown Ge layer by a novel technique of two-step etching with polymerization in between. Ge-nanowires (GeNWs) with diameter down to 14 nm were integrated with the TaN/High-k gate stack to form Ge nanowire pMOSFETs. The on/off ratio as high as 6 orders at -1.2 V VDS was achieved on the 14 nm diameter Ge nanowire transistor. However, hole field effect mobility was low due to the surface roughness scattering and the Coulomb scattering caused by the heavy interface state trap density. To improve the GeNW surface topology, Epitaxial-Si over GeNW was employed. The Ge/Si core/shell nanowires were integrated with the TaN/HfO2 gate stack to form GAA GeNW pMOSFETs. With the introduction of the Si epitaxial shell, the Ge nanowire transistor performance was significantly improved. A 200 nm gate length Ge/Si core/shell nanowire GAA pMOSFET demonstrated high on-state current of 150 ?A/?m, a peak field effect mobility of 254 cm2/V-s, and a backscattering coefficient of 0.31.||URI:||http://scholarbank.nus.edu.sg/handle/10635/25831|
|Appears in Collections:||Ph.D Theses (Open)|
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