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https://scholarbank.nus.edu.sg/handle/10635/247284
DC Field | Value | |
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dc.title | EXPLORATION OF GALLIUM OXIDE DEVICES FOR POWER APPLICATIONS | |
dc.contributor.author | HE MINGHAO | |
dc.date.accessioned | 2024-02-29T18:00:39Z | |
dc.date.available | 2024-02-29T18:00:39Z | |
dc.date.issued | 2023-08-05 | |
dc.identifier.citation | HE MINGHAO (2023-08-05). EXPLORATION OF GALLIUM OXIDE DEVICES FOR POWER APPLICATIONS. ScholarBank@NUS Repository. | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/247284 | |
dc.description.abstract | Beta gallium oxide (β-Ga<sub>2</sub>O<sub>3</sub>) is an emerging candidate for the next generation of power devices, particularly Schottky barrier diode (SBD) and metal-oxide-semiconductor field-effect transistors (MOSFET). However, the development of Ga<sub>2</sub>O<sub>3</sub> power device fabrication is still at its early stage. This thesis addresses and proposes solutions for issues that are still problems for Ga<sub>2</sub>O<sub>3</sub> based devices. The first part of the thesis demonstrates a method to improve the SBD’s subthreshold slope (61 mV/dec) and uniformity across the wafer by inserting an Al-reacted interfacial layer between the metal and semiconductor. Despite the exceptional characteristics of the Ga<sub>2</sub>O<sub>3</sub> SBD, the lack of p-type Ga<sub>2</sub>O<sub>3</sub> is preventing it from achieving even higher voltage blocking capability. In the second part, solutions to achieve p-type alternatives for Ga<sub>2</sub>O<sub>3</sub> are investigated, including heterojunctions based on NiO<sub>x</sub>/Ga<sub>2</sub>O<sub>3</sub> and Ga<sub>2</sub>O<sub>3</sub>/p-GaN, and current blocking layer based on Mg-Ga<sub>2</sub>O<sub>3</sub>. The unipolar operation characteristic of Ga<sub>2</sub>O<sub>3</sub> also raises concerns for Ga<sub>2</sub>O<sub>3</sub>-based metal-oxide-semiconductor field-effect-transistor (MOSFET), as conventional Ga<sub>2</sub>O<sub>3</sub> MOSFET typically operate in depletion-mode (D-mode). In the final segment of the thesis, an innovative approach is presented, which introduces an enhancement-mode (E-mode) Ga<sub>2</sub>O<sub>3</sub> MOSFET based on charge trapping layer (CTL) technique. | |
dc.language.iso | en | |
dc.subject | Ga<sub>2</sub>O<sub>3</sub>, power device, SBD, MOSFET, fabrication, semiconductor | |
dc.type | Thesis | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.contributor.supervisor | Kah Wee Ang | |
dc.contributor.supervisor | Yu Hongyu | |
dc.description.degree | Ph.D | |
dc.description.degreeconferred | DOCTOR OF PHILOSOPHY (CDE-ENG) | |
dc.identifier.orcid | 0000-0001-5249-6480 | |
Appears in Collections: | Ph.D Theses (Open) |
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File | Description | Size | Format | Access Settings | Version | |
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HeMH.pdf | 5.81 MB | Adobe PDF | OPEN | None | View/Download |
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