Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/23792
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dc.titleDesign and implementation of a high speed and low power flash ADC with fully dynamic comparators
dc.contributor.authorLI TI
dc.date.accessioned2011-07-01T18:01:12Z
dc.date.available2011-07-01T18:01:12Z
dc.date.issued2010-01-20
dc.identifier.citationLI TI (2010-01-20). Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/23792
dc.description.abstractThis work mainly focuses on design and implementation of a high speed low power flash ADC with fully dynamic comparators. For flash ADC design, fully dynamic comparator offers several very desirable attributes, like high speed and low power consumption. As a result, a significant improvement of overall performance is expected. The primary issue with implementing fully dynamic comparators is its large offset variation. We have first designed, implemented and tested a background offset calibration technique with a two stage comparator structure. While the second stage is fully dynamic, the first stage is not so as to provide a linear range for the convenience of adjusting its offset voltage. Chopper is used at the input to isolate offset from the input signal, so that it can later be extracted by a digital LPF. A proto type chip fabricated in AMS 0.35um CMOS technology has demonstrated its effectiveness. With 23 comparators tested, all of their offset voltages are brought down to below 0.8mV, while its initial value can be as high as above 20mV. This technique is further developed for its application in fully dynamic comparators, which is used in a 6 bit 500MHz flash ADC design implemented in IBM 0.13um CMOS technology. MOS caps are inserted to the fully dynamic comparator's critical nodes to provide linear calibration, while using the same extraction technique. 63 fully dynamic comparators used in this ADC are background calibrated in a serial manner with a proposed general control scheme so as to reduce chip size. To optimize the calibration technique, SAR search algorithm is adopted for the calibration of each comparator, instead of linear search algorithm initially used in the comparator's case. Simulation result has shown that the entire flash ADC, including T&H circuit, resistor ladder and encoder, consumes only 9.5mW of power at 500MHz.
dc.language.isoen
dc.subjectlow power, flash ADC, fully dynamic comparators, background calibration, high speed, offset voltage
dc.typeThesis
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.contributor.supervisorLIAN YONG
dc.contributor.supervisorYAO LIBIN
dc.description.degreeMaster's
dc.description.degreeconferredMASTER OF ENGINEERING
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Master's Theses (Open)

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