Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/23150
Title: A framework to explore low-power architecture and variability-aware timing estimation of FPGAs
Authors: LEE CHEE SING
Keywords: FPGA, VPR, Affine, process variations, reconfigurable
Issue Date: 18-May-2007
Citation: LEE CHEE SING (2007-05-18). A framework to explore low-power architecture and variability-aware timing estimation of FPGAs. ScholarBank@NUS Repository.
Abstract: This thesis is written in 3 main sections. First, a new CAD tool is developed to facilitate the design of arbitrary FPGA architectures with the help of a graphical user interface. Placement and routing capabilities are added to test the designed architecture. Second, we use the developed framework to investigate an alternative approach to minimize the short-circuit power of FPGA global interconnects. A reconfigurable buffer is designed and integrated in the switch block. From our simulation, the proposed architecture reduces the dynamic power by 6.10% - 10.06% compared to conventional architecture. Third, we use a developed framework VPR to explore variability-aware timing estimation of FPGAs. Correlation-aware affine arithmetic is used to model the timing uncertainties. Compared to Monte Carlo simulations, the mean of our timing variation is within 1% accuracy, the average looseness range is about 22.6% and 4.5% for the Uniform and Gaussian distribution respectively; and a 1000X simulation speed-up.
URI: http://scholarbank.nus.edu.sg/handle/10635/23150
Appears in Collections:Master's Theses (Open)

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