Investigation of high-K gate dielectrics for advanced CMOS application

Abstract

Timely implementation of high-k gate dielectric will involve dealing with four major challenging issues: (1) thermal instability, (2) mobility degradation, (3) charge trapping induced Vth instability, and (4) Fermi level pinning caused high Vth. The main purpose of this thesis was to overcome the four major challenges, and also attempts to integrate the high-k gate dielectrics to conventional self-aligned poly-Si gate and advanced metal gate processes. In Chapter 2, we proposed a novel HfTaO gate dielectric with good thermal stability. Advanced HfTaON/SiO2 gate stack with superior carrier mobility and excellent Vth stability was presented in Chapter 3. The effective suppression of Fermi Level pinning by using poly-SiGe/high-k structure was demonstrated in Chapter 5. Several serious integration issues of high-k were discussed in Chapter 4 and 6. The studies may contribute to a good understanding of material properties, electrical characteristics and reliability in high-k gate dielectric for advanced CMOS application.