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|Title:||Novel devices for enhanced CMOS performance||Authors:||CHUI KING JIEN||Keywords:||Strained, Tensile, Compressive, SiGe, SiC||Issue Date:||16-May-2007||Citation:||CHUI KING JIEN (2007-05-16). Novel devices for enhanced CMOS performance. ScholarBank@NUS Repository.||Abstract:||Aggressive CMOS transistor scaling has driven CMOS transistors into the nanoscale regime, making it the most widespread nanotechnology in production today. Further transistor scaling becomes increasingly challenging and faces many difficulties related to physical limitations. A new and emerging trend is the exploration of alternative ways to enhance CMOS transistor performance besides size reduction. The main focus will be on different schemes to form strained silicon transistors for enhanced performance over conventional silicon CMOS transistors where the silicon is not strained. When the crystal lattice of silicon is strained, the electronic properties of silicon will be modified. By engineering the strain introduced, the strain-induced modification of electronic properties can be made to improve the mobility of carriers (i.e. electrons and holes) in silicon. This leads to a higher drive current for CMOS transistors and a corresponding increase in speed of integrated circuits formed using these transistors. Faster integrated circuit speed enables new products or applications with faster computational power or increased functionality||URI:||http://scholarbank.nus.edu.sg/handle/10635/23050|
|Appears in Collections:||Ph.D Theses (Open)|
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