Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/224572
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dc.titlePARALLEL GRAPH PROCESSING ACCELERATORS ON FPGAS
dc.contributor.authorCHEN XINYU
dc.date.accessioned2022-04-30T18:00:41Z
dc.date.available2022-04-30T18:00:41Z
dc.date.issued2021-12-16
dc.identifier.citationCHEN XINYU (2021-12-16). PARALLEL GRAPH PROCESSING ACCELERATORS ON FPGAS. ScholarBank@NUS Repository.
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/224572
dc.description.abstractGraphs are de facto data structures to represent different relationships of entities in many emerging big data applications, e.g., data science and machine learning. The exponential growth of data from these applications has created a pressing demand for high-performance graph processing. Subsequently, graph processing systems have become a hot research topic in academia and industry. Despite a wealth of existing efforts in developing graph processing systems for improving the performance and/or energy efficiency of traditional architectures, graph processing accelerators are essential and emerging to provide benefits significantly beyond what pure software solutions can offer. In this thesis, we tackle the core challenge of designing FPGA-based graph processing accelerators with HLS and then propose ThunderGP to improve both the performance and the programmability of FPGA-based graph processing. Finally, we propose ReGraph to scale graph processing on HBM-enabled FPGA platforms by improving the resource efficiency of accelerators with heterogeneous pipelines.
dc.language.isoen
dc.subjectGraph Processing, FPGA, Hardware Accelerator, HLS, Architecture, Framework
dc.typeThesis
dc.contributor.departmentCOMPUTER SCIENCE
dc.contributor.supervisorBingsheng He
dc.description.degreePh.D
dc.description.degreeconferredDOCTOR OF PHILOSOPHY (SOC)
dc.identifier.orcid0000-0003-1951-5015
Appears in Collections:Ph.D Theses (Open)

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