Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/224572
Title: PARALLEL GRAPH PROCESSING ACCELERATORS ON FPGAS
Authors: CHEN XINYU
ORCID iD:   orcid.org/0000-0003-1951-5015
Keywords: Graph Processing, FPGA, Hardware Accelerator, HLS, Architecture, Framework
Issue Date: 16-Dec-2021
Citation: CHEN XINYU (2021-12-16). PARALLEL GRAPH PROCESSING ACCELERATORS ON FPGAS. ScholarBank@NUS Repository.
Abstract: Graphs are de facto data structures to represent different relationships of entities in many emerging big data applications, e.g., data science and machine learning. The exponential growth of data from these applications has created a pressing demand for high-performance graph processing. Subsequently, graph processing systems have become a hot research topic in academia and industry. Despite a wealth of existing efforts in developing graph processing systems for improving the performance and/or energy efficiency of traditional architectures, graph processing accelerators are essential and emerging to provide benefits significantly beyond what pure software solutions can offer. In this thesis, we tackle the core challenge of designing FPGA-based graph processing accelerators with HLS and then propose ThunderGP to improve both the performance and the programmability of FPGA-based graph processing. Finally, we propose ReGraph to scale graph processing on HBM-enabled FPGA platforms by improving the resource efficiency of accelerators with heterogeneous pipelines.
URI: https://scholarbank.nus.edu.sg/handle/10635/224572
Appears in Collections:Ph.D Theses (Open)

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