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Title: Design of a low-power dual-rail asynchronous 8051 microcontroller
Authors: XUE CHAO
Keywords: Asynchronous, 8051, low-power, dual-rail, microcontroller, asychronous-synchronous interface
Issue Date: 21-Jul-2010
Citation: XUE CHAO (2010-07-21). Design of a low-power dual-rail asynchronous 8051 microcontroller. ScholarBank@NUS Repository.
Abstract: In this thesis, the design of a low-power voltage-scalable asynchronous 8051 microcontroller is presented. It is targeted to function as a general purpose processing unit in a biomedical sensor interface system with a possibly varying supply voltage in the range of 1V to 3.3V. At the top level, the proposed asynchronous 8051 microcontroller can be divided into four major parts: the asynchronous 8051 core, the synchronous peripherals, the custom-designed asynchronous SRAM and the interface wrapper blocks. The design flow starts from coding the asynchronous 8051 core using a dedicated hardware description language in the Balsa framework. After passing behavioral verification, the HDL code is synthesized into a Verilog gate-level netlist by the Balsa framework. This Verilog gate-level netlist of the asynchronous core is then read in by the Synopsys Design Compiler together with other Verilog modules that describe the interface blocks and synchronous peripherals. The Design Compiler optimizes and compiles the individual Verilog files into a unified Verilog gate-level netlist, which is then imported into the Cadence SOC Encounter together with the LEF (library exchange format) file of the custom-designed asynchronous SRAM block for automatic P&R (placement and routing). A GDS (graphical database system) file of the asynchronous 8051 microcontroller is exported from the SOC Encounter into the Cadence Virtuoso framework. After performing LPE (layout parasitic extraction), the SPICE netlist is passed to Nanosim for final post-layout simulation verification. The asynchronous 8051core is synthesized using an asynchronous EDA tool called ¿Balsa¿ and it adopts the four-phase dual-rail protocol. Four different versions of the asynchronous core are developed during the master candidature. According to the Nanosim post-layout transistor-level simulation data, the last version (referred as Design 4 in this thesis) consumes about 166pJ per each instruction while running at around 0.42MIPS at 1.0V supply for AMS 0.35µm technology. It is able to function properly from the nominal supply voltage of 3.3V down to 1V and below. The proposed novel interface block to external commercial memory can work with any commercial memory in general after proper configuration of the preset overflow value and driving clock frequency of an internal counter module inside the interface block.
Appears in Collections:Master's Theses (Open)

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